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D Flip Flop Example D (Delay) Flip Flop is edge triggered, i.e. output will only change during a rising or falling clock edge. Basically the Flip Flop output follows the D input at a one clock delay
Mux/Demux Example The Mux/Demux block can be configured as either a multiplexer of demultiplexer. In Mux mode, the vlock rotates through all inputs, passing one signal at a time. The switch rate can be controlled eithe rinternally or externally. In Demux mode, the block routes the recieved signal in a rotating fashion to each of its outputs.
Parallel to Serial Example The Parallel to Serial block generates the output clock internally at the user specified rate. The first output bit in each group of serial buts is made to coincide with the incoming symbol clock. Subsequent bits are clocked out at the specified rate. If the output rate is too fast, then gaps will result sin the output
"Due to its power, flexibility, ease-of-use, and low cost, VisSim has been Carrier's choice for system modeling, simulation, data acquisition, and rapid prototyping for over eight years." Mr. Richard Kolk - Manager Simulation & Control Technology
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